Design closure

Results: 169



#Item
111Integrated circuits / Electronic design / Digital electronics / Signoff / Timing closure / Physical design / Design closure / Integrated circuit design / Compiler / Electronic engineering / Electronic design automation / Electronics

Datasheet IC Compiler Comprehensive Place and Route System Overview

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Source URL: www.synopsys.com

Language: English - Date: 2015-03-05 12:15:39
112Road transport / Traffic signs / Law enforcement / Road safety / Speed limit / Design speed / National Maximum Speed Law / Warning sign / Speed limits in the United States / Transport / Land transport / Traffic law

D[removed]SIGN LAYOUT FOR ONE LANE CLOSURE TWO LANE ROADWAY W20[removed]G20-55-96

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Source URL: www.dot.nd.gov

Language: English - Date: 2013-10-02 14:53:36
113Road transport / Traffic signs / Law enforcement / Road safety / Speed limit / Warning sign / National Maximum Speed Law / Design speed / Speed limits in the United States / Transport / Land transport / Traffic law

D[removed]CONSTRUCTION SIGN LAYOUT Non-signalized Low Volume One Lane Closure R2-1-48

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Source URL: www.dot.nd.gov

Language: English - Date: 2013-10-02 14:53:35
114Hardware verification languages / Hardware description languages / Logic design / SystemVerilog / Debugging / E / Logic simulation / VHDL / Timing closure / Electronic engineering / Electronic design automation / Digital electronics

Datasheet Verdi3 Automated Debug System Overview

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Source URL: www.synopsys.com

Language: English - Date: 2015-01-20 19:15:21
115Electronic design / Integrated circuits / Digital electronics / Field-programmable gate array / Xilinx / Logic synthesis / Application-specific integrated circuit / Timing closure / Synopsys / Electronic engineering / Electronics / Electronic design automation

Success Story Synopsys and Teradici ASIC Prototyping Made Fast and Efficient with Synplify Premier Other tools can’t handle the complex constructs of the ASICs we’re working

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Source URL: www.synopsys.com

Language: English
116Application-specific integrated circuit / Synopsys / Field-programmable gate array / Timing closure / FPGA prototype / Logic synthesis / Catapult C / Electronic engineering / Electronic design automation / High-level synthesis

Success Story Synopsys and STMicroelectronics Rapid Delivery of Demodulator IP for Analog TV Standards using Synphony Model Compiler High-Level Synthesis Solution

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Source URL: www.synopsys.com

Language: English
117Electronic design automation / Integrated circuits / Logic design / Electronic circuits / Hillsboro /  Oregon / Synopsys / Timing closure / Field-programmable gate array / Analog-to-digital converter / Electronic engineering / Electronics / Digital electronics

Success Story Synopsys and Stellamar All-Digital ADC a Design Success with SPW Algorithm Design Tool Synopsys is a key partner in helping us innovate. Synopsys SPW gives us the

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Source URL: www.synopsys.com

Language: English
118Pharmacology / Drug safety / Scientific method / Science / Institutional review board / Clinical research / Research / Design of experiments

CENTRAL DEPARTMENT OF ENERGY INSTITUTIONAL REVIEW BOARD (CDOEIRB) Human Subjects Research Request for Project Closure (FWA00015568) This form must be submitted in typed form and all applicable items must be answered. Ple

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Source URL: humansubjects.energy.gov

Language: English - Date: 2012-08-29 10:08:10
119Containers / Industrial engineering / Industrial design / Packaging and labeling / Retailing / Containerization / International Air Transport Association / Closure / Sample / Technology / Business / Transport

LLC, TESTING 314 Fort CherryRoad McDonald,PA[removed]infofEhishollc.com REPORT TO:

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Source URL: www.nphl.org

Language: English - Date: 2012-01-30 14:13:25
120Electronic design / Integrated circuits / Fabless semiconductor companies / Field-programmable gate array / Logic synthesis / High-level synthesis / Timing closure / Altera / Integrated circuit design / Electronic engineering / Electronics / Electronic design automation

Datasheet Synplify Premier Fast, Reliable FPGA Implementation and Debug Overview

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Source URL: www.synopsys.com

Language: English - Date: 2015-01-28 12:16:00
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